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Design and implementation of configurable floating-point vector multiplication unit based on FPGA

基于FPGA的可配置浮点向量乘法单元设计实现

Huang Zhaowei

Wang Lianming

edge computing

parallel computing

FPGA

configurable

floating-point vector multiplication

No. 9, 2020 : 2762-2765,2771 doi:10.19734/j.issn.1001-3695.2019.04.0141

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Search浮点向量乘法returned 1 results

Design and implementation of configurable floating-point vector multiplication unit based on FPGA